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DSP Builder Handbook
Chapter 7: Using the Interfaces Library
Avalon-ST Interface
The Avalon Interface Specifications define how to convey data between a source
interface and a sink interface. The interface indicates the integrity of the data by a feed
forward signal, valid . The specification also defines how the MegaCore functions
may stall other blocks (backpressure) or regulate the rate at which you provide data
with a feedback sideband signal, ready .
You can configure the DSP Builder Avalon-ST Source and Avalon-ST Sink blocks
with a ready latency of 0 or 1. The ready latency is the number of cycles that a source
must wait after a sink asserts ready so that a data transfer is possible. The source
interface provides valid data at the earliest time possible, and it holds that data until
sink asserts ready. The ready signal notifies the source interface that it has sampled
the data on that clock cycle.
For the ready_latency = 0 mode, Figure 7–12 shows the interaction that occurs between
the source interface valid signal and the sink interface ready signal.
Figure 7–12. Avalon-ST Interface Timing for ready-latency=0
On cycle one, the source provides data and asserts valid even though the sink is not
ready . The source waits until cycle two and the sink acknowledges that it samples the
data by asserting ready . On cycle three, the source happens to provide data on the
same cycle that the sink is ready to receive it and so the transfer occurs immediately.
On the fourth cycle, the sink is ready but because the source does not provide any
valid data, the data bus is not sampled.
A beat is the transfer of one unit of data between a source and sink interface. This unit
of data may consist of one or more symbols, so it can support modules that convey
more than one piece of information on each valid cycle. Some modules have parallel
input interfaces and other instances require serial input interfaces. For example, when
conveying an in-phase and quadrature component on the same clock cycle. The choice
depends on the algorithm, optimization technique, and throughput requirements.
November 2013 Altera Corporation
Volume 2: DSP Builder Standard Blockset
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